1. Field of the Invention
The field of this invention relates generally to direct conversion receivers, and, more specifically, to subharmonic frequency translators for use in such receivers, and preprocessors for improving the switching characteristics of the LO input to such frequency translators.
2. Background
Conventional receivers downconvert a radio frequency (RF) signal to baseband frequencies in two steps. In the first step, the signal is downconverted to intermediate frequencies (IF), and in the second step, the signal is downconverted to baseband frequencies. A conventional receiver is illustrated in FIG. 1. An RF signal 1 having a carrier frequency FRF is applied to RF input port 3 of mixer 2. A signal 10 having a frequency FX less or greater than FRF originating from local oscillator (LO) 9 is passed through bandpass filter 15 and then through a low noise amplifier (LNA) (not shown). The resulting signal is then applied to the LO input port 4 of mixer 2. The mixer 3 mixes the two signals and provides an output signal at output port 5. The output signal has two principal frequency components: one at the frequency FRFxe2x88x92FX (or FXxe2x88x92FRF in the case in which FX is greater than FRF), the so-called intermediate or IF frequency FIF, and the other at the frequency FRF+FX.
The signal is passed through IF filter 6 which substantially attenuates the component at the frequency FRF+FX, thus leaving the intermediate frequency component. The output of the filter including this intermediate frequency component is identified with numeral 7.
This signal is provided to the signal input port of mixer 8. At the same time, a signal 12 at the same intermediate frequency and originating from local oscillator 12 is applied to the LO input port of mixer 8. Mixer 8 mixes the signals provided at its two inputs, and produces an output signal having two principal frequency components: one at the frequency 2FIF, and the other at zero or baseband frequencies FBB. The output of the mixer 8 is passed through baseband filter 14 which substantially attenuates the component at the frequency 2FIF, thus leaving the component at baseband frequencies. The output of the filter is identified in the figure with numeral 13.
Direct conversion receivers downconvert an RF signal to baseband frequencies in a single step. Typically, a mixer mixes an RF signal with an LO signal at the same frequency as the carrier of the RF signal. The mixer produces two primary frequency components in the output signal: one at the difference frequency FRFxe2x88x92FLO, and the other at the frequency FRF+FLO. Since the LO signal is at the same frequency at the RF signal, the first such component is at baseband frequencies, and the second such component is at high frequencies.
The output of the mixer is passed through a baseband filter, which substantially attenuates the high frequency component of the output, leaving the baseband component. Compared to the conventional receiver of FIG. 1, direct conversion receivers eliminate components such as the IF filter 6, one of the mixers, and one of the local oscillators. The elimination of the IF filter is particularly advantageous because such filters tend to be bulky, expensive, and not implementable on-chip.
However, direct conversion receivers are typically limited in their sensitivity because of leakage from the LO port to the RF port, or leakage of large RF blockers from the RF port to the LO port, both of which can result in self-mixing, and introduction of a large unwanted DC component in the output signal.
Subharmonic mixers are mixers in which the LO frequency is a subharmonic of the RF frequency. Subharmonic mixers allow generation of lower frequency LO signals, which eases synthesizer and voltage controlled oscillator (VCO) design. They also provide the potential for frequency isolation between the LO and RF signals.
Unfortunately, most subharmonic mixers have relatively low conversion gain and high noise as compared to standard mixers. They are also plagued by the presence, on an internal node or pin, of LO harmonics which, because they are at the mixing frequency, can still self-mix to DC. Some also require bulky transformers that limit or prevent on-chip implementation. Most also have substantially non-linear RF transfer functions.
The Gilbert mixer is one type of mixer which allows for conversion gain. However, conventional Gilbert mixers include a mixer core which is unable to accommodate a LO frequency which is a subharmonic of the RF frequency.
More specifically, the standard Gilbert mixer is driven by an LO signal having two components which are 180xc2x0 are of phase with respect to one another. The components are clipped in order to increase the transition times thereof, thereby improving noise performance and achieving a higher conversion gain. However, such techniques cannot be generalized to the subharmonic mixer case.
Therefore, there is a need for a direct conversion receiver with increased gain, noise performance, and sensitivity compared to the prior art.
There is also a need for a subharmonic mixer which is capable of on-chip implementation, has conversion gain, noise figure, and linearity characteristics comparable to or exceeding those of conventional mixers, and does not generate on an internal pin or node LO harmonics at the mixing frequency.
There is also a need for a preprocessor which improves the switching characteristics of successive phase-split LO inputs.
In accordance with the purpose of the invention as broadly described therein, there is provided a direct conversion receiver comprising a subharmonic frequency translator configured to receive a phase-split LO input. In one embodiment, the receiver also includes a preprocessor for preprocessing the phase-split LO inputs to improve the switching characteristics thereof. An example application of such a receiver is within a mobile communications device or handset in a wireless communications system.
A first aspect of the invention comprises the frequency translator. A second aspect comprises the preprocessor. A third aspect comprises the frequency translator in combination with the preprocessor. A fourth aspect comprises the direct conversion receiver. A fifth aspect comprises a wireless communications system including a wireless communications device which includes the direct conversion receiver of the subject invention.
In one embodiment, the frequency translator comprises: a first input for receiving a first input signal; at least one input for receiving a phase-split second input signal having 2n components, wherein n is an integer greater than 1; first and second outputs; a frequency translator core configured to switch the first input signal to the first output responsive to assertion of any of a first group of components of the phase-split input signal, and configured to switch the first input signal to the second output responsive to assertion of any of a second group of components of the phase-split input signal.
In one implementation, the first group comprising alternate ones of the components of the phase-split input signal, and the second group comprising the remaining components of the phase-split input signal.
Each of the 2n components of the seconnd input signal can be one of a plurality of 2n single-ended signals, or a component of one of a plurality of n differential signals, each having positive phase and negative phase components. To avoid confusion, and to allow usage of a common terminology in this specification, both cases will be described in terms of a phase-split input signal having 2n components.
Similarly, the signals produced on the first and second outputs may each be single-ended signals, or may be components of a differential output signal. The two may remain as separate signals or components, as the case may be, or may be combined to form a single-ended output signal.
In addition, the first input signal may either be a single-ended input signal or one of the components of a differential input signal. In one implementation, the first input signal is one of the components of a differential input signal, and the frequency translator core is configured to switch the other component of the differential input signal to the second output responsive to assertion of any of the first group of components of the phase-split input signal, and is configured to switch the other component of the differential input signal to the first output responsive to assertion of any of the second group of components of the phase-split input signal.
In another embodiment, the frequency translator is a multiplier having first and second inputs, and first and second outputs. The multiplier is configured to alternate, at a frequency which is about 1/n times the frequency of the second input, wherein n is an integer greater than 1, between switching the first input to the first output, and the first input to the second output, all while substantially avoiding physically generating on an internal node or pin a signal having a frequency about equal to n times the frequency of the second input. In one embodiment, the signals formed at the first and second outputs, which can either be single-ended output signals or components of a differential output signal, are combinable into a signal which is representative of the product of the first signal and a multiplication factor which switches polarity at about n times the frequency of the second signal.
In one implementation, the frequency translator is a mixer having RF and LO inputs, and a differential mode output having positive and negative phase components. The mixer has a mixer core which is configured to switch polarity, i.e., alternate between switching the RF input to the positive phase component of the output, and switching the RF input to the negative phase component of the output, at a frequency which is about n times the LO frequency, wherein n is an integer greater than 1. In one embodiment, a single-ended output is formed by combining the positive and negative phase components of the differential output. In one implementation example, the frequency of the LO input is about 1/n times the frequency of the RF input.
In one embodiment, a signal applied to the second input of the mixer has a period T, and the mixer is configured to alternate, at a rate of about T/2n, wherein n is an integer greater than 1, between 1) switching the first input signal to the positive phase component of the output, and 2) switching the first input signal to the negative phase component of the output. In one embodiment, each of these steps is performed during consecutive but substantially non-overlapping subperiods of the period T, each of the subperiods having a duration of about T/2n, where n is an integer greater than 1.
In a second embodiment, the first input signal is a differential mode signal having positive and negative phase components, and the mixer is configured to alternate, at a rate of about T/2n, between 1) switching the positive phase component of the first input to the positive phase component of the output while switching the negative phase component of the first input to the negative phase component of the output; and 2) switching the negative phase component of the first input to the positive phase component of the output while switching the positive phase component of the first input to the negative phase component of the output.
In either of these embodiments, the signals produced at the output may be kept in differential mode, or alternatively, may be combined to form a single-ended output signal.
In one implementation, the mixer is a modified Gilbert mixer. In one implementation example, the modified Gilbert mixer receives a differential RF input, and provides a differential output. In this implementation example, the mixer core comprises 4n bipolar NPN transistors in two logical groups of 2n transistors each. The differential RF input is a current mode input having positive and negative components. The positive component is coupled to the emitters of the transistors in the first group, and the negative component is coupled to the emitters of the transistors in the second group.
The collectors of the odd-numbered transistors in the first group are coupled together to form a first node, and the collectors of the even-number transistors in the first group are coupled together to form a second node. The collectors of the even-numbered transistors in the second group are coupled to the first node, and the collectors of the odd-numbered transistors in the second group are coupled to the second node.
The differential output is a current mode output having positive and negative components. The positive component of the output is taken from the first node, and the negative component of the output is taken from the second node.
The LO input is an evenly phase-split voltage mode signal provided by the preprocessor. The signal has 2n components split about 180/n degrees apart. Each of the components is in a predefined state sufficient to trigger a switching action of the mixer core for a time about equal to T/2n during a period T, where T is the period of the LO signal. Only one of the components is in the predefined state at a time. The ith component of the phase-split input is coupled to the base of the ith transistor in each group.
In one configuration, n=2, and the LO frequency is about xc2xd the RF carrier frequency. In this configuration, the mixer core switches polarity at about twice the LO frequency. This configuration employs what is known as one-half LO injection. In a second configuration, n greater than 2.
In one embodiment, the preprocessor provides the preprocessed phase-split LO input responsive to a phase-split LO input. In this embodiment, the preprocessor comprises limiter circuitry and arithmetic circuitry. The limiter circuitry limits each of the components of the input to form a limited signal, and the arithmetic circuitry arithmetically combines the components of the limited signal to form the preprocessed phase-split LO signal which is input to the mixer. In one embodiment, the limiter circuitry limits the components of the input signal by amplifying and then clipping them such that each of the components resembles a square wave.
In one implementation, the limiter circuitry limits each component of the phase-split input signal to form a square wave, and the arithmetic circuitry pairwise combines the square waves to form the input signal to the mixer.
Implementation examples are possible in which any of the differential mode signals in the foregoing examples are single-ended signals, or in which any of the foregoing current mode signals are voltage mode, and vice-versa. Further implementation examples are possible in which the transistors in the mixer core comprise or embody bipolar PNP transistors, MOSFETs, HBTs, BJTs, CMOS technology, HEMTs, MODFETs, diodes, MESFETs, JFETs, or the like.
A method of operation of a direct conversion receiver in accordance with the subject invention comprises the steps of receiving a first input; providing a phase-split second input at a frequency which is about I/n times the frequency of the first input, wherein n is an integer greater than 1; preprocessing the second input to improve the switching characteristics thereof, using the preprocessed input to alternate, at a frequency which is about n times the frequency of the second input, between 1) switching the first input to a first output; and 2) switching the first input to a second output. In one embodiment, the method further comprises combining the signals produced at the two outputs to form a single-ended output, and then filtering the single-ended output signal to recover the baseband component thereof.
One embodiment of a method of mixing first and second input signals in accordance with the subject invention, the second signal having a period T, comprises alternating the following steps at a rate of about 2n/T, wherein n is an integer greater than 1: 1) switching the first signal to a first output; and 2) switching the first signal to a 3second output.
In another embodiment, a method of operation of a frequency translator in accordance with the subject invention comprises alternating, at a rate of about 2n/T, wherein T is the period of an LO input, and n is an integer greater than 1, between the steps of: 1.) switching an RF signal to a positive phase component of a differential output; and 2.) switching the RF signal to the negative phase component of the output.
In a third embodiment, wherein the RF input is a differential mode input having positive and negative phase components, RF+and RFxe2x88x92, respectively, and the output is a differential mode output having positive and negative phase components, output+and outputxe2x88x92, respectively, the method comprises alternating, at a rate of about 2n/T, between the steps of: 1.) switching RF+ to output+ while switching RFxe2x88x92 to outputxe2x88x92; and 2.) switching RFxe2x88x92 output+ while switching RF+ to outputxe2x88x92.
One embodiment of a circuit for improving, in accordance with the subject invention, the switching characteristics of a phase-split input signal having 2n components, wherein n is an integer greater than 1, comprises: limiter circuitry for limiting the components of the input signal to produce a limited phase-split signal; and arithmetic circuitry for arithmetically combining the components of the limited phase-split signal to produce an output phase-split signal having improved switching characteristics in relation to the input signal, the output signal having 2n components.
A second embodiment comprises circuitry for receiving a phase-split input signal having a period T and also having 2n components, wherein n is an integer greater than 1; and circuitry for producing therefrom a phase-split output signal, also having a period T, and also having 2n components, such that 1) for each substantially non-overlapping T/2n subperiod of the period T, only one of the components of the output signal is asserted at a time, and a different one of the components is asserted in each of the subperiods, 2) each of the components is substantially symmetric about a horizontal axis, 3) the transitions times between the on and off states of each of the components are fast. In one implementation, each of the components of the output signal has a stairstep shape For purposes of this disclosure, assuming that a component of the output signal achieves an amplitude A in the 2n/T period in which it is asserted, a fast transition is one in which the transistion occurs at a rate equal to or exceeding (A+2n)/T. Also for purposes of this disclosure, a signal is asserted when it is placed in a predefined state which, in one embodiment, is the state which is sufficient to trigger a mixer to switch polarity. In one implementation, a signal is asserted when it is the highest signal at a time.
A method of preprocessing a phase-split input to form a phase-split output, the input having a period T and also having 2n phase-split components, wherein n is an integer greater than 1, comprises the steps of: limiting the components of the input to form a phase-split limited signal; and arithmetically combining the components of the limited signal to form a phase-split output signal.
The advantages of a direct conversion receiver in accordance with the subject invention include greater sensitivity compared to a conventional direct conversion receiver, a lower LO frequency, reduced LO and RF coupling, and ease of design stemming from the reduced LO and RF coupling.
The advantages of a subharmonic mixer in accordance with the subject invention, compared to a conventional subharmonic mixer, include reduction in the unwanted DC component in the output signal caused by self-mixing of the LO or RF input signals. Leakage from the LO to the RF ports is at the actual LO frequency, while the frequency of the original LO signal is effectively increased n times due to the switching action of the mixer. The result is that unwanted mixing will occur between a signal at the LO frequency, and a signal at about n times the LO frequency. Since the two are substantially different, little or no baseband components will result.
Leakage from the RF to the LO ports, which is nominally at the RF frequency, is effectively increased in frequency n times due to the switching action of the mixer. The frequency of the original RF signal remains the same, however. The result is that unwanted mixing will occur between a signal at the RF frequency, and a signal at about n times the RF frequency. Again, since the two are substantially different, little or no baseband component will occur.
Still another advantage is on-chip manufacturability given that, in one embodiment, all the components of the mixer core are transistors, and transistors are easily implementable on-chip.
Yet another advantage, compared to conventional subharmonic mixers, is a more linear RF transfer function given that, through the switching action of the mixer, the RF+ and RFxe2x88x92 currents are alternatively steered directly to the outputs of the mixer.
Finally, yet another advantage of the mixer of the subject invention is that, because it is similar in topology to a Gilbert mixer, a great deal of pre-existing experience can be brought to bear, thus speeding design.
An advantage of the preprocessor of the subject invention is a phase-split LO signal having steeper transitions between the on and off states thereof compared to a sinusoidal LO phase-split signal. When used to drive a mixer, such transitions result in improved mixer gain, improved mixer noise performance, and therefore improved mixer sensitivity.
Another advantage of the preprocessor of the subject invention is a phase-split signal in which the transitions between on and off state are defined by LO zero crossings, which provides better rejection of RF self-mixing, and less dependence on LO amplitude matching, and the type and shape of the LO waveform.
An advantage of the combination of the subharmonic mixer and the preprocessor of the subject invention compared to a subharmonic mixer driven by a sinusoidal phase-split LO signals is low conversion loss given that virtually all the RF input current is retained in the output.
Another advantage of such a combination is reduced noise and sensitivity to interference due to the steeper transitions between the on and off states of the preprocessed phase-split LO inputs.